Kingston Technology Corp. KSM56R46BD8PMI-48MBI 48GB DDR5-5600 CL46 2Rx8 Registered server RAM
- 48 GB
- DDR5 5600
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64GB DDR4 2400MHz ECC LRDIMM 4Rx4 server memory module with CL17 latency and 1.20V operation
This 64GB module provides high-capacity DDR4 memory for server and workstation systems that require error-correcting code and load-reduced technology. It operates at 2400MHz with a CAS latency of CL17 and a standard voltage of 1.20V. The 4Rx4 rank configuration and Micron chipset ensure dependable performance for demanding workloads.
The DDR4 2400MHz standard limits this module to a maximum transfer rate of PC4-19200. Systems with memory controllers that only support lower DDR4 speeds will downclock the module, while platforms requiring higher speeds cannot utilise its full rated frequency. The 288-pin DIMM form factor fits only compatible DDR4 server slots.
The 4Rx4 load-reduced design places an electrical buffer on the module to reduce signal loading on the memory bus, allowing higher densities per channel. This architecture is mandatory for systems that require LRDIMM topology and will not function in platforms limited to standard RDIMM or UDIMM populations. Buyers needing single-rank or standard registered modules cannot use this part.
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| Product | |
|---|---|
| Brand name | A-Tech |
| Product line | Compatible Replacement for Micron |
| Model name | MTA72ASS8G72LZ-2G3A1PG, MTA72ASS8G72LZ-2G3B2PK |
| Total capacity | 64 GB |
| Performance | |
| Rated speed | DDR4 2400 (PC4 19200) |
| Processor | |
| Chipset | Micron Chipset |
| Memory | |
| CAS latency | CL17 |
| ECC support | Yes |
| Buffer type | Load Reduced |
| Memory rank | 4Rx4 |
| Power | |
| Rated voltage | 1.2 V |
This module is a single 64GB DDR4 2400MHz ECC LRDIMM with a 4Rx4 organisation, designed for servers that support Load Reduced DIMMs.
The module runs at 2400 MT/s with CL17 latency at 1.20V, delivering the standard DDR4 2400 data rate for ECC-protected workloads.
The 288-pin DDR4 DIMM form factor carries the 2400 MT/s signal and ECC LRDIMM protocol; the platform’s memory controller determines the final operating speed.
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